Voltage-to-analog pulse rate converter

ABSTRACT

A circuit is provided for converting a relatively slowly varying DC voltage value to a proportional repetitive pulse train. The circuit is especially adapted to monitoring some quantity or physical value that can be represented by a direct current input voltage when it is desired to transmit for some distance, the monitored value, without loss of accuracy in the initial measurement. The pulse train can be transmitted without change in frequency to a remote readout device.

U Umted States Patent 1151 3,643,113 Brock et al. 1 Feb. 15., 1972 [54] VOLTAGE-TO-ANALOG PULSE RATE 3,386,039 5/1968 Naive ..328/127 CONVERTER 3,422,372 1/1969 Post et al. .333/111 3,283,057 11 1966 Cam bell ..307/271 [72] Inventors: Gordon L. Brock; Charles 11. Armstrong, p

both ofHuntlngton Beach, Callf. 0TH ER PU BlJCATlONS I73] Assigncc: Hersey-Sparling Meter Company, El

M m calif "Period of Sawtooth Ramp Extends to 5 Hours by Ron I22] med: Mar-7,1969 Chapmamone page, Replmt flom EiLLllUlllLS June 7 l 66 [21] Appl. No: 805,321 Primary Examiner-Donald D. Forrer Assistant Examiner-Harold A. Dixon Attorney-Donald Diamond [52] US. Cl ..307/271, 328/127, 307/235,

331/177, 307/228 57] ABSTRACT [51] lnt.Cl. ..H03k 4/56 581 Field of Search ..328/127;331/1 11, 177; A PrQWde01 for convemng a relatwely Slowly varymg 307 2 1 271 235 2 DC voltage value to a proportional repetitive pulse train. The circuit is especially adapted to monitoring some quantity or [5 References Cited physical value that can be represented by a direct current input voltage when it is desired to transmit for some distance, UNITED STATES PATENTS the monitored value, without loss of accuracy in the initial measurement. The pulse train can be transmitted without Mcwhlrter et change in frequency to a remote readout device.

3,060,388 10/1962 ..33l/1l1 1 Claim, 2 Drawing Figures 3,219,945 11/1965 ...333/1l1 3,256,426 6/1966 ...328/127 3,274,501 9/1966 Heinsen ..328/127 7 5 fimgrrwe 7W W f/VVf/PIZ/P P0485 PM 85 fA/pur GZ/l/A'A /I 70/? fl/LWATOR SHAPE/Q 0077307.

+3ov E w L. 1|. L* 22} 21 Our/ aT Q i Q 9 i jX/Puf R25 6 l l D 1 COM 1 i T i i COM I 1 l VOLTAGE-TO-ANALOG PULSE RATE CONVERTER BACKGROUND OF THE INVENTION The present invention relates generally to electronic voltage to pulse rate converters and more particularly to an electric circuit for generating pulses with a pulse repetition rate substantially directly proportional to a varying input voltage value.

In many telemetering applications, it is desirable to reduce the signal attenuation or other adverse effect of the transmission medium by varying a parameter of the telemetering signal which is independent of the transmission medium. For some applications, this is most easily effected by employing a pulse train as the telemetering signal and varying the repetition rate of the pulses in accordance with the measured quantity. Thus, the transmission medium may distort the shape and amplitude of the individual pulses of the pulse train, but the repetition rate will remain unaffected.

In certain applications, the measured quantity may vary relatively slowly, requiring time periods of the order of hours and minutes for substantial changes to occur. In such cases, it is desirable, for economic reasons, to use the lowest grade transmission medium possible. In order to utilize advantageously such low grade transmission media with pulsetrain-type telemetering signals, the pulse repetition rate must be relatively low in order to insure effective transmission of the pulse signal. Additionally, the pulse signal itself must be of sufficient amplitude and of sufficiently long duration that an individual pulse is transmitted through the medium without intolerable distortion of the pulse wave shape.

In the past, electronic circuitry for converting a relatively slowly changing input voltage value to a pulse train output of relatively low pulse repetition rates have in many cases suffered from an internal instability over the relatively long periods of time over which they are operated. To compensate for these internal instabilities, relatively expensive compensating circuitry has been employed which was not actually a part of the converting circuitry.

SUMMARY OF THE INVENTION To solve the stability problems in electronic circuitry for converting an input voltage value to an output pulse train with a pulse rate substantially directly proportional to the input voltage value, the present invention provides an improved voltage-to-pulse-rate converter. The converter utilizes electronic circuit means which are either inherently relatively selfstabilizing or which operate in a substantially switching mode. The input voltage governs only one of the operating parameters of the electronic circuit means which produces the output pulse train.

A ramp-generating means generates a voltage ramp and the input voltage value determines only the slope of the ramp. When the ramp voltage reaches a predetermined value, the ramp is reset to an initial value by a resetting means. An output pulse is generated in response to resetting of the ramp generating means.

In a presently preferred embodiment of the voltage-topulse-rate converter, an operational amplifier connected essentially in an integrating mode is utilized to generate a substantially linear voltage ramp across an integrating capacitor. A resetting means in the form of a threshold voltage sensing circuit utilizing a unijunction transistor is connected across the integrating capacitor to reset the capacitor to an initial value when a predetermined threshold voltage is reached. The pulses generated by the triggering of the unijunction transistor are fed to a pulse shaping circuit to develop output pulses of substantially constant amplitude and duration which are substantially longer than the pulses generated by the triggering of the unijunction transistor.

The repetition rate of the generated pulses is substantially directly proportional to the input voltage value.

BRIEF DESCRIPTION OF THE DRAWING FIG. I is a block diagram of the voltage-to-pulse rate converter embodying the present invention; and

FIG. 2 is a schematic diagram of the voltage-to-pulse rate converter.

DESCRIPTION OF A PREFERRED EMBODIMENT Referring now to the drawing, particularly FIG. I, the presently preferred embodiment of the voltage-topulse rate converter may be conveniently described as comprising four sections. The input voltage is fed to a lz-I inverter l0 which not only inverts the polarity of the input voltage but serves to effectively isolate the input terminals from the remainder of the circuitry. The output of the inverter 10 corresponds substantially to the voltage value of the input but is of opposite polarity and is fed to a ramp generator [2. The ramp generator 12 generates a substantially linear voltage ramp with the slope of the ramp determined by the value of the voltage appearing at the output of the inverter 10.

The voltage ramp appearing at the output of the ramp generator is connected to a resetting pulse generator 14 containing a threshold device which resets the voltage ramp to an initial value when the ramp voltage reaches a predetermined level. As the ramp is reset, a pulse substantially coincident in time is generated.

The pulse appearing at the output of the pulse generator 14 is a relatively short spike unsuitable for the low-grade transmission mediums in which the described embodiment of the converter is to be used so the sharp pulse output of the pulse generator is fed to a pulse shaper 16 which changes the sharp pulse to one with a relatively rectangular waveshape of a substantially predetermined height and duration. The height and duration of the output pulse from the pulse shaper 16 are selected to be suitable for transmission through a low-grade transmission medium without suffering distortions severe enough to defeat its utility.

Typically, the described preferred embodiment of the voltage-to-pulse-rate converter is adapted to receive a relatively slowly varying positive DC voltage of from O to 8 volts. The output frequency of the converter is variable from 0 to ap' proximately 20 pulses per second and is substantially proportional to the instantaneous input voltage value.

Referring now to FIG. 2, the inverter '10 of the converter is generally an operational amplifier with the input and feedback resistances adjusted so that the gain of the amplifier is substantially unity or one. As will become apparent, the operational amplifier is constructed so that the input voltage is inverted in polarity. Resistor R, serves as an input resistor to the opera tional amplifier and the combination of fixed resistor R and variable resistor R serve as the feedback resistance network, The junctions of input and feedback resistors R,, R and R, are connected to the input of the combination of transistors 0,, Q and Q and their associated circuitry.

Diode D, is connected between the junction of the input and feedback resistors R, and R respectively, and the common reference point with the cathode of Diode D, connected to the common reference point. As is well known, the voltage appearing between the junction of the resistors R, and R and the common reference point of the operational amplifier is substantially zero for proper operation, and this voltage is below the forward voltage drop of D, so that for normal operation, D, is not conducting. Should a spike of input voltage appear at the input, however, the operational amplifier may not be able to respond fast enough, and D, serves as a protection against damage.

Transistors Q1, Q2, and Q, are connected in a generally known operational amplifier configuration with parallel matched transistor 0, serving as a differential amplifier driving cascaded direct-coupled transistors Q2 and Q Resistors R R and R serve as the collector resistors for one side of Q,, Q and 0,, respectively, which are all connected to a 20- volt source of positive potential. Resistor R, is connected from the common emitter junction of O to a source of 20-volt negative potential, in conformance with generally known operational amplifier configurations.

As the input to the operational amplifier varies only between and 8 volts, the output of the amplifier need vary only between 0 and -8 volts. Therefore, the capability of conventional operational amplifiers of varying both positively and negatively is not needed, and the circuitry needed to generate a positive output voltage has been deleted from the inverter of the preferred embodiment shown.

To this end, 0 is connected in an emitter-follower configuration with the resistors R and R forming a voltage-dividing network providing a suitable input to the base of transistor 0 which is essentially connected to a Class A amplifier with Q. conducting current through its collector circuit substantially over the entire range of input voltages. Resistor R is the collector-resistor for Q and resistor R serves-as the emitterbiasing resistor. The values of resistors R, and R as well as the ratio of the resistors R and R in the voltage divider are adjusted so that when zero input voltage is applied, the output of the operational amplifier appearing at the collector of O is essentially at the common reference level. As the input voltage increases positively, transistor Q is driven further into conduction drawing the collector toward the 20-volt source and increasing the negative voltage of the output with respect to the common point.

Diode D is connected across the output of the operational amplifier of the inverter to prevent the output from going in a positive direction and capacitor C is also connected across the output to filter out any noise form the input voltage or the operational amplifier itself.

The ramp generator 12 of the converter is basically an operational amplifier connected in an integrating configuration with resistor R as the input resistor and capacitor C as the feedback capacitor. The input to resistor R is connected to the output pointof the inverter l0 which is the collector of Q Again, the junction of input resistor R and feedback capacitor C is connected to an input base of a parallel matched transistor 0 connected as a differential amplifier. Collector resistors R and R are connected between a 20- volt source of positive potential and the collectors of Q A fixed resistor R and a variable resistor R serve as the emitter resistor for the commonly connected emitters of Q Resistors R, and R are thus connected in series to a -volt source of negative potential. The input base of transistor 0,; is directly connected to one collector of differential amplifier Q with resistor R serving as the collector resistor of Q Feedback capacitor C is connected between the output of the operational amplifier which is the collector of Q and the input base of Q Resistor R and Diode D are connected between the input base of Q and the common reference point with the cathode of Diode D connected to the input base.

As the negative voltage of a particular value is applied to R from the inverter 10, the collector of Q moves in a positive direction supplying a current which charges capacitor C The charging current is applied to the input base of Q and a small positive voltage appears across R Diode D is therefore reverse biased when C is charging and no current flows through it. The relationship between the current feedback and the gain of the operational amplifier is such that a constant current is applied to capacitor C thereby causing a linearly increasing ramp voltage to appear across its terminals.

Following conventional operational amplifier-integrating circuit theory, the slope of the ramp voltage developed across capacitor C is substantially directly proportional to the input voltage supplied by the inverter 10. The larger the value of the input voltage, the steeper the slope of the ramp voltage.

The linearly increasing ramp voltage appearing at the collector of O is also applied to the emitter of unijunction transistor 0 A relatively small capacitor C is also connected between the emitter of Q and the common reference point to insure proper triggering of Q The base-to-base voltage for unijunction transistor 0, is derived from the 20-volt source of positive potential through a resistor R to base one of Q and a relatively small resistor R from base two of O to the common terminal point. It will be appreciated that in this configuration, unijunction transistor 0-, functions as a threshold device in that the emitter-tobase two impedance is relatively high until the emitter-to-base two voltage reaches a certain level. At that threshold point, the emitter-to-base two impedance drops sharply and the unijunction transistor Q, triggers.

When the ramp voltage across C plus a relatively small positive voltage appearing across R reaches the threshold level of Q Q, is triggered and the emitter-to-base two resistance decreases greatly. Capacitor C, then discharges through the emitter-to-base two junction of 0, through R and Diode D which causes Diode D to be forward biased. Capacitor C also discharges through the emitter-to-base two junction of Q, and resistor R but as capacitor C is relatively small in value compared to capacitor C capacitor C essentially controls the discharge rate.

As is well known, a capacitor discharging through the triggered emitter-to-base two junction of a unijunction transistor would create a relatively short and peaked current pulse through resistor R generating a voltage pulse across that resistor. As this pulse is of too short a duration to be transmitted efficiently through a low'grade transmission medium, the short duration pulse is fed to the pulse shaper 16. The pulse shaper 16 generates a pulse of considerably higher voltage and considerably longer duration in response to the output pulse from the triggered unijunction transistor 0 The pulse shaper 16 is basically a direct coupled amplifier utilizing transistors Q and Q The collector resistor R of O is connected to the 20-volt source of positive potential and the collector resistor R of O is connected to a 30-volt source of positive potential, The emitters of both transistors 0,, and 0 are connected to the common reference point. The output of the amplifier is derived between the collector of Q. and the common reference point.

The input circuit for the pulse shaper is a resistor R in series with a capacitor C connected between the input base of Q and the common reference point. The output pulse from the triggered unijunction transistor 0, is fed to the junction of R and C through a Diode D The gain of Q is such that when the pulse through Diode D charges capacitor C the current through R from C 4 and the base emitter junction of 0,, is more than sufficient to saturate transistor Q dropping its collector voltage near that of the common reference point. This in turn cuts off transistor Q thus raising the voltage at the output terminal to substantially the 30-volt positive source. lt will be appreciated that the leading slope of the positive going output pulse is substantially coincident with the pulse derived from the triggered unijunction Q The current required to maintain O in saturation is quite low and capacitor C while discharging, maintains 0,, in saturation for a longer period of time than the duration of the pulse derived from the unijunction transistor 0 The configuration of the latter pulse for the preferred embodiment illustrated is approximately 20 milliseconds. Also, the small amount of current needed to maintain O in saturation is such that the rate of change of the current from discharging capacitor C is high enough so that the time required to turn transistor Q off once it has begun conducting is relatively short compared to the length of time that Q is saturated. Therefore, the waveshape of the output pulse appears substantially rectangular in shape.

To adjust the voltage-to-pulse rate converter for proper operation, the input voltage is set at zero, and variable resistor R is adjusted so that no voltage ramp is generated by the ramp generator 12. The input voltage is then set at some predetermined value and feedback resistor R in the inverter 10 operational amplifier is adjusted so that the output pulse repetition rate is proportional to the predetermined input voltage.

Typical component values for the voltage-to-pulse-rate converter are as follows:

0. 2N2223 A (or matched pair of 2N3565l 0.. 2N2223 A (or matched pair of ZN 3565 C, (M mld. (lotto-v) C, 0.047 mm. (25wv) R lOlt ohms R, 8.2l: ohms R, 5k ohms (pot) R, (will: ohms R, 410 ohms R 47 ohms R llllt ohms R ISOlt ohms R 68k ohms R 8.2lt ohms it Hi ohm R 470 ohms R 82k ohms R 4.7lt ohms It will be understood that while the presently preferred embodiment of the invention has been described and illustrated,

modifications of design and construction can be made without departing from the spirit and scope of the invention. Therefore, the above description of a specific embodiment is considered to be illustrative of rather than limitative upon the invention disclosed herein.

We claim:

I. An electrical circuit for generating uniform repetitive output pulses having a repetition rate analogous to an input voltage level, said circuit comprising: electrical integrating means for integrating saidinput voltage level to produce a voltage ramp having a slope substantially proportional to said input voltage level said integrating means including an operational amplifier having input and output terminals and a common reference terminal, said operational amplifier having a capacitor connected between said output and input terminals. said operational amplifier further having a first resistor connected between said input terminal and a second resistor connected between said input terminal and said common reference terminal. said operational amplifier further having a diode with its anode connected to said input terminal and its cathode connected to said common reference terminal;

means for resetting saidvoltage ramp of said integrating means to an initial value when said voltage ramp reaches a predetermined voltage level said resetting means including a unijunction transistor having an emitter and first and second bases, said first base being connected to a source of positive potential through a third resistor and said second base being connected to said common reference terminal through a fourth resistor, the emitter of said unijunction transistor being connected to said output terminal of said operational amplifier for discharging said capacitor at least initially through said diode, the emitter-to-base two circuit of said unijunction transistor and said fourth resistor when the voltage across said capacitor reaches the predetermined emitter threshold voltage of said unijunction transiston'and means responsive to the resetting of said voltage ramp for generating an output pulse having a predetermined wave shape. 

1. An electrical circuit for generating uniform repetitive output pulses having a repetition rate analogous to an input voltage level, said circuit comprising: electrical integrating means for integrating said input voltage level to produce a voltage ramp having a slope substantially proportional to said input voltage level said integrating means including an operational amplifier having input and output terminals and a common reference terminal, said operational amplifier having a capacitor connected between said output and input terminals, said operational amplifier further having a first resistor connected between said input terminal and a second resistor connected between said input terminal and said common reference terminal, said operational amplifier further having a diode with its anode connected to said input terminal and its cathode connected to said common reference terminal; means for resetting said voltage ramp of said integrating means to an initial value when said voltage ramp reaches a predetermined voltage level said resetting means including a unijunction transistor having an emitter and first and second bases, said first base being connected to a source of positive potential through a third resistor and said second base being connected to said common reference terminal through a fourth resistor, the emitter of said unijunction transistor being connected to said output terminal of said operational amplifier for discharging said capacitor at least initially through said diode, the emitter-to-base two circuit of said unijunction transistor and said fourth resistor when the voltage across said capacitor reaches the predetermined emitter threshold voltage of said unijunction transistor; and means responsive to the resetting of said voltage ramp for generating an output pulse having a predetermined wave shape. 